Generally, a computer system""s main memory has not been subject to data compression. An emerging development in computer organization is the use of data compression in a computer system""s main memory, where data in the main memory itself is stored in a compressed format.
A trend in computer architectures is to aggregate the largest possible number of functional components within the package of the processor chip. Hence, architectures in which the memory controller resides on the same chip as the processor would have advantages of reducing communication delays between the processor and the memory controller and of permitting a single-chip package. A potential disadvantage, however, is the limited amount of space available on the processor chip.
More specifically, a large portion of the processor chip space is typically devoted to the level-2 (xe2x80x9cL2xe2x80x9d) cache, which is usually as large as possible. Hence, there is usually not enough additional space for further caches, such as a line buffer, directory cache and/or level-3 (xe2x80x9cL3xe2x80x9d) cache. Additionally, the number of pins available on a chip is finite, and most of the pins on a processor chip are already used, and cannot be spared to connect the memory controller to an external cache and/or buffer. With no directory cache and/or L3 cache, the latency associated with memory fetches can be large.
These and other drawbacks and disadvantages of the prior art are addressed by a computer system and corresponding method for supporting a compressed main memory.
The computer system includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register.
The corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memory line corresponding to the cache line being written, writing the content of the cache line into the appropriate position in the memory line, compressing the data contained in said memory line, and storing the compressed data into the compressed main memory, and, if the cache miss is a cache read miss: retrieving the compressed data corresponding to the compression translation table address from the compressed main memory and decompressing the retrieved data.
These and other aspects, features and advantages of the present disclosure will become apparent from the following description of exemplary embodiments, which is to be-read in connection with the accompanying drawings.